1. Field of the Invention
The present invention relates to a circuit for generating a data strobe signal (DQS) in a DDR memory device and a method therefor, and more particularly to, a circuit for generating a DQS in a DDR memory device which can precisely control preamble and postamble periods of the input/output DQS, and a method therefor.
2. Discussion of Related Art
As publicly known, a synchronous DRAM (SDRAM) synchronized with an external system clock has been widely used to improve an operation speed among the semiconductor devices. The general SDRAM uses only a rising edge of a clock, but the DDR SDRAM uses both rising and falling edges of a clock to improve an operation speed. Therefore, the DDR SDRAM is expected as a next generation DRAM. On the other hand, a data strobe signal (DQS) is used to minimize a time skew generated between chips of a memory chip set during the data read operation. The DQS will now be briefly explained.
FIG. 1 is a waveform diagram illustrating the DQS.
FIG. 1 shows timing in the data read operation of the DDR SDRAM, especially when CAS latency (CL) for defining a clock number from a read command input clock time point to a data output time point is 2 and when a burst length (BL) for defining a number of consecutively-processed data is 4.
In the read operation of the DDR SDRAM, when the DQS is enabled, the data must be outputted in the rising and falling edges. Here, the DQS must pass through a preamble state before one clock from data output, and pass through a postamble state for half a clock even after last data output.
Before the preamble state, the DQS may maintain a high impedance (high-z) state which is an intermediate level between high and low states, or maintain a high level in a ultrahigh speed memory device such as the GDDR III. In this case, it is difficult to set or distinguish the preamble or postamble period of the DQS. Especially, an operation margin is reduced due to a high operation speed. It is thus more difficult to precisely set the preamble or postamble period of the DQS. As a result, the data read operation is not efficiently performed.